Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /CGU /PLL_CLK_SEL

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Interpret as PLL_CLK_SEL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)SYSREF 0 (Val_0x0)SYS 0 (Val_0x0)ES0 0 (Val_0x0)ES1

SYSREF=Val_0x0, ES0=Val_0x0, ES1=Val_0x0, SYS=Val_0x0

Description

PLL Clock Select Register

Fields

SYSREF

Select the source for SYST_REFCLK

0 (Val_0x0): Select oscillator clock source

1 (Val_0x1): Select PLL clock source

SYS

Select the source for CPUPLL_CLK and SYSPLL_CLK

0 (Val_0x0): Select oscillator clock source

1 (Val_0x1): Select PLL clock source

ES0

Select the source for RTSS_HP_CLK

0 (Val_0x0): Select a value specified by the ESCLK_SEL[ES0_OSC] field

1 (Val_0x1): Select a value specified by the ESCLK_SEL[ES0_PLL] field

ES1

Select the source for RTSS_HE_CLK

0 (Val_0x0): Select a value specified by the ESCLK_SEL[ES1_OSC] field

1 (Val_0x1): Select a value specified by the ESCLK_SEL[ES1_PLL] field

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